The present invention relates to an instruction supply mechanism for use in a computer system.
In a computer system, instructions are typically fetched from a program memory, decoded and supplied to an execution unit where they are executed to run the program stored in the program memory. It is advantageous for such a computer system to be able to support more than one instruction mode. A novel computer system described herein can support three instruction modes.
According to a first instruction mode, during each machine cycle a pair of 16 bit instructions are supplied to the decoder.
According to a second instruction mode, during each machine cycle two 32 bit instructions are supplied to the decoder. According to a third instruction mode, four 32 bit instructions are supplied to the decode unit during each machine cycle.
In order to manage these different instruction modes, the decode unit has a plurality of dedicated decoders each of which receives and decodes a bit sequence during each machine cycle. Depending on the instruction mode of the machine, the outputs of selected ones of the decoders are supplied to the execution units for execution. The outputs of the other decode units are not required.
It is an aim of the invention to reduce power consumption by preventing unnecessary activity by the decoders which are not selected for use in the particular instruction mode in which the machine is operating.
According to one aspect of the invention there is provided an instruction supply mechanism for supplying instructions to a decoder, the instruction supply mechanism comprising:
a set of output devices, each having an input and an output and capable of transferring a parallel sequence of bits from the input to the output;
read circuitry for supplying to the inputs of the output devices sequences of bits representing instructions to be decoded;
each output device having a stop switch which selectively connects to the input of that output device either its output or the read circuitry in dependence on the state of a stop control signal.
According to another aspect of the invention there is provided a processor comprising:
at least one execution unit for executing instructions;
an instruction mode indicator which indicates one of a plurality of instruction modes for the processor;
a decoder for decoding instructions prior to dispatch to the at least one execution unit; and
an instruction supply mechanism for supplying instructions to the decoder, the instruction supply mechanism comprising:
a set of output devices each having an input and an output and capable of transferring a parallel sequence of bits from the input to the output;
read circuitry for supplying to the inputs of the output devices sequences of bits representing said instructions to be decoded in accordance with the indicated instruction mode; and
wherein each output device has a stop switch which selectively connects to the input of that output device either its output or the read circuitry in dependence on the state of a stop control signal.
With the above-defined features, unused outputs are automatically recirculated towards the decoders to prevent different decoders from unnecessarily consuming power.
In order to cope with changes in instruction modes, the instruction supply mechanism can additionally include a change mode switch associated with a first one of said output devices. The change mode switch is responsive to a first change mode signal to selectively connect the input of the first output device to either the read circuitry or the output of a second one of the output devices.
The read circuitry can comprise a set of read ports corresponding respectively to the output devices.
The second output device can additionally have a second change mode switch responsive to a second change mode signal to selectively connect the input of the second output device either to the output of the read port associated with the first output device or the read port associated with the second output device.